Semiconductor device

ABSTRACT

First and second IP cores are formed on one chip. Each of the first and second IP cores has metal layers. In the first IP core, an uppermost layer of the metal layers is thick and is a layer on which a core power source line is formed. In the second IP core, a metal layers equal in level to the uppermost layer in the first IP core becomes an intermediate layer. In the second IP core, thin intermediate layers are formed on this intermediate layer. Thin intermediate layers are layers on which signal lines are formed and have a narrow wiring pitch. In the second IP core, a layer on which a power source line is formed is provided on the thin intermediate layers.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is based upon and claims the benefit of priorityfrom the prior Japanese Patent Application No. 2000-297670, filed Sep.28, 2000, the entire contents of which are incorporated herein byreference.

BACKGROUND

[0002] The present invention relates to a semiconductor device having amultilayer wiring structure. The present invention is particularlyapplied to a system LSI manufactured using an IP core.

[0003] The recent development of the process technique has acceleratedthe microstructure and high integration of semiconductor elements.Following them, it has become possible to mount an entire system on onechip. A circuit constituting the system is, however, large in scale andcomplicated. To design such a circuit from a gate level, considerableresources are required, which is disadvantageous in efficiency.

[0004] To enhance LSI design efficiency including the above-stateddisadvantage, a design method for recycling past design properties andassembling them on a chip for a general-purpose block is graduallyspread.

[0005] Meanwhile, such design properties are referred to as IP's(Intellectual Properties), stored as an IP core in a library and freelypicked up as required.

SUMMARY

[0006] A semiconductor device according to the aspect of the presentinvention comprises a lowermost layer nearest to a semiconductorsubstrate, an uppermost layer farthest from the semiconductor substrateand intermediate layers arranged between the lowermost layer and theuppermost layer. If assuming that one of the intermediate layers is thefirst intermediate layer and the other one is the second intermediatelayer, the first intermediate layer is on the lowermost layer sidecompared with the second intermediate layer and thicker than the secondintermediate layer.

[0007] The first intermediate layer comprises a first area having signallines and a second area having power source lines, and a pitch of thepower source lines is wider than that of the signal lines. And the firstintermediate layer comprises a first area having signal lines and asecond area having power source lines, and a width of each of the powersource lines is wider than that of the signal lines.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008]FIG. 1 shows an IP core;

[0009]FIG. 2 is a cross-sectional view showing the device structure ofthe IP core shown in FIG. 1;

[0010]FIG. 3 shows a chip on which the IP core shown in FIG. 1 ismounted;

[0011]FIG. 4 is a cross-sectional view showing the structure of asemiconductor device shown in FIG. 3;

[0012]FIG. 5 shows an IP core;

[0013]FIG. 6 is a cross-sectional view showing the device structure ofthe IP core shown in FIG. 5;

[0014]FIG. 7 shows a chip on which the IP core shown in FIG. 5 ismounted;

[0015]FIG. 8 is a cross-sectional view showing the structure of asemiconductor device shown in FIG. 7;

[0016]FIG. 9 shows an IP core;

[0017]FIG. 10 is a cross-sectional view showing the device structure ofthe IP core shown in FIG. 9;

[0018]FIG. 11 shows a chip on which the IP core shown in FIG. 9 ismounted;

[0019]FIG. 12 is a cross-sectional view showing the structure of asemiconductor device shown in FIG. 11;

[0020]FIG. 13 shows an IP core;

[0021]FIG. 14 is a cross-sectional view showing the device structure ofthe IP core shown in FIG. 13;

[0022]FIG. 15 shows a chip on which the IP core shown in FIG. 13 ismounted;

[0023]FIG. 16 is a cross-sectional view showing the structure of asemiconductor device shown in FIG. 15;

[0024]FIG. 17 shows a chip on which the IP core shown in FIG. 9 and theIP core shown in FIG. 13 are mounted;

[0025]FIG. 18 is a cross-sectional view showing the structure of asemiconductor device shown in FIG. 17;

[0026]FIG. 19 shows an IP core;

[0027]FIG. 20 is a cross-sectional view showing the device structure ofthe IP core shown in FIG. 19;

[0028]FIG. 21 shows a chip on which the IP core shown in FIG. 19 ismounted;

[0029]FIG. 22 is a cross-sectional view showing the structure of asemiconductor device shown in FIG. 21;

[0030]FIG. 23 shows an IP core;

[0031]FIG. 24 is a cross-sectional view showing the device structure ofthe IP core shown in FIG. 23;

[0032]FIG. 25 shows a chip on which the IP core shown in FIG. 23 ismounted;

[0033]FIG. 26 is a cross-sectional view showing the structure of asemiconductor device shown in FIG. 25;

[0034]FIG. 27 shows a chip on which the IP core shown in FIG. 19 and theIP core shown in FIG. 23 are mounted;

[0035]FIG. 28 is a cross-sectional view showing the structure of thesemiconductor device shown in FIG. 27;

[0036]FIG. 29 shows the comparison between the present invention and areference example in respect of the length of a wiring layer; and

[0037]FIG. 30 shows a chip on which four IP cores are mounted.

DETAILED DESCRIPTION

[0038] Semiconductor device of the present invention will be hereinafterdescribed with reference to the drawings.

[0039] 1. Reference Example

[0040] First, description will be given to a reference example whichforms a basis for the present invention.

[0041]FIG. 1 shows an IP core. FIG. 2 shows one example of the devicestructure of the IP core shown in FIG. 1.

[0042] In this example, the IP core is realized by three metal layersM1, M2 and M3. These metal layers M1, M2 and M3 have the same thicknessand formed into thin wiring layers. If this IP core is used during adesign phase, the metal layers M1, M2 and M3 are used as they are. Inaddition, as shown in FIGS. 3 and 4, metal layers M4 and M5 are added,thereby forming a predetermined functional block (circuit) in a chip.

[0043] Here, the metal layer M4 is a thin wiring layer as in the case ofthe metal layers M1, M2 and M3. The metal layer M5 is thicker than themetal layers M1, M2, M3 and M4 and formed into a thick wiring layer. Itis noted that the metal layer M5 which is the uppermost layer is usedas, for example, a chip power source line.

[0044] Recently, there are a demand for, for example, providing a powersource line on the intermediate layer of a semiconductor device and ademand for transferring signals at high speed. Due to this, it isdesired that the thickness of the intermediate layer (e.g., the metallayer M3) of the semiconductor device is made almost equal to thethickness of the uppermost layer (metal layer M5).

[0045] To do so, IP core is necessary to change the structure shown inFIGS. 1 and 2 to that show in FIGS. 5 and 6.

[0046] In the reference example, however, if the metal layer M3 of theIP core is made thicker as shown in FIGS. 5 and 6 and a semiconductordevice is formed using this IP core, then all the metal layers on themetal layer M3, i.e., the metal layers M4 and M5 are also made to beformed into thick wiring layers as shown in FIGS. 7 and 8.

[0047] In that case, the wiring pitches of the metal layers M3, M4 andM5 naturally widen, with the result that the number of wirings (thenumber of signal lines, in particular) cannot be disadvantageouslyincreased on the layers on the metal layer M3.

[0048] Further, in case of an ordinary semiconductor device, only theuppermost layer (metal layer M5) is a thick wiring layer and theremaining metal layers (metal layers M1, M2, M3 and M4) are thin wiringlayers. As shown in FIGS. 5 and 6, therefore, if the metal layer M3 ofthe IP core is made thick, this IP core cannot be used for designingsuch an ordinary semiconductor device and the semiconductor device mustbe designed from the beginning.

[0049] 2. First Embodiment

[0050]FIG. 9 shows an IP core. FIG. 10 shows one example of the devicestructure of the IP core shown in FIG. 9.

[0051] In this embodiment, the IP core (IP1) is realized by three metallayers M1, M2 and M3. The metal layers M1 and M2 of the IP core aremainly used as signal lines and formed into thin wiring layers. Theuppermost layer (metal layer) M3 of the IP core is mainly used as a corepower source line, thicker than the metal layers M1 and M2 and formedinto a thick wiring layer.

[0052] In this embodiment, it is assumed that the metal layers M1 and M2have the same wiring width. Also, the metal layer M3 has a large widthon a portion used as, for example, a core power source line and a smallwiring width on portions used as signal lines as shown in FIG. 10 as inthe case of the metal layers M1 and M2. It is noted that the portion ofthe metal layer used as the core power source line may have a smallwidth.

[0053] If this IP core is used in a design phase, the metal layers M1,M2 and M3 are used as they are. In addition, as shown in FIGS. 11 and12, metal layers M4 and M5 are added, thereby providing a predeterminedfunction block (circuit) in the chip.

[0054] Here, the metal layer M4 is mainly used as signal lines andformed into a thin wiring layer as in the case of the metal layers M1and M2. The uppermost layer (metal layer) M5 of the semiconductor deviceis mainly used as a chip power source line and pad metal and formed intoa thick wiring layer as in the case of the metal layer M3.

[0055] As can be seen, the semiconductor device according the presentinvention is characterized in that at least one of the intermediatelayers (wiring layers excluding the uppermost and lowermost layers)among a plurality of wiring layers is constituted out of a thick filmand that at least one wiring layer on the at least one intermediatelayer is constituted out of a thin film.

[0056] In other words, in the reference example, the thick wiring layeris formed on the thin wiring layer and no thin wiring layer is formed onthe thick wiring layer. According the present invention, by contrast, athin wiring layer can be formed on the thick wiring layer as required.

[0057] As a result, if the uppermost layer of the IP core is constitutedout of a thick film to use the uppermost layer of the IP core as, forexample, a core power source line, a wiring layer used as signal linesfurther above the uppermost layer of the IP core can be constituted outof a thin film in the semiconductor device using this IP core.

[0058] Furthermore, the core power source line can enhance theperformance of the IP core (functional block) and enables the wiringlayer on the uppermost layer of the IP core to be constituted out of athin film. Due to this, wiring efficiency can be enhanced and optimum IPdesigning and product development can be carried out.

[0059] 3. Second Embodiment

[0060]FIG. 13 shows an IP core. FIG. 14 shows one example of the devicestructure of the IP core shown in FIG. 13.

[0061] The IP core (IP2) in this embodiment has a function differentfrom that of, for example, the IP core (IP1) shown in FIGS. 9 and 10.However, the number of metal layers and the thicknesses of therespective metal layers are common to the both IP cores.

[0062] The IP core (IP1) is realized by three metal layers M1, M2 andM3. The metal layers M1 and M2 of the IP core are mainly used as signallines and formed into thin wiring layers. The uppermost layer (metallayer) M3 of the IP core is mainly used as a core power source line,thicker than the metal layers M1 and M2 and formed into a thick wiringlayer.

[0063] In this embodiment, it is assumed that the metal layers M1 and M2have the same wiring width. In addition, the metal layer M3 has a largewidth on a portion used as the core power source line and a small wiringwidth on parts used as signal lines as in the case of the metal layersM1 and M2 as shown in FIG. 14. It is noted that the portion of the metallayer used as the core power source line may have a small width.

[0064] If this IP core is used in a design phase, the metal layers M1,M2 and M3 are used as they are and, as shown in FIGS. 15 and 16, metallayers M4 and M5 are added, thereby forming a predetermined functionalblock (circuit) in the chip.

[0065] Here, the metal layer M4 is mainly used as signal lines andformed into a thin wiring layer as in the case of the metal layers M1and M2. On the other hand, the uppermost layer (metal layer) M5 of thesemiconductor device is mainly used as a chip power source line and padmetal and formed into a thick wiring layer as in the case of the metallayer M3.

[0066] As can be seen, the semiconductor device according to the presentinvention is characterized in that at least one of the intermediatelayers (wiring layers excluding the uppermost and lowermost layers)among a plurality of wiring layers is constituted out of a thick filmand that at least one wiring layer on the at least one intermediatelayer is constituted out of a thin film.

[0067] That is, in the reference example, the thick wiring layer isformed on the thin wiring layer and no thin wiring layer is formed onthe thick wiring layer. According to the present invention, by contrast,a thin wiring layer can be formed on the thick wiring layer as required.

[0068] As a result, even if the uppermost layer of the IP core isconstituted out of a thick film so as to use the uppermost layer of theIP core as a core power source line, a wiring layer used as signal linesfurther above the uppermost layer of the IP core can be constituted outof a thin film in the semiconductor device using this IP core.

[0069] Furthermore, the core power source line can enhance theperformance of the IP core (functional block) and enables the uppermostwiring layer of the IP core to be constituted out of a thin film. Due tothis, wiring efficiency can be enhanced and optimum IP designing andproduct development can be carried out.

[0070] Meanwhile, according to the present invention, the IP core (IP1)shown in FIGS. 9 and 10 and the IP core (IP2) shown in FIGS. 13 and 14have the common number of wiring layers and the common thicknesses ofthe respective wiring layers. Accordingly, as shown in FIGS. 17 and 18,even if the IP core (IP1) and the IP core (IP2) are mounted on onesemiconductor chip to constitute one semiconductor system, the layoutsof the respective IP cores can be utilized as they are. Therefore,design efficiency is enhanced and semiconductor device developmentperiod can be thereby shortened.

[0071] 4. Third Embodiment

[0072]FIG. 19 shows an IP core. FIG. 20 shows one example of the devicestructure of the IP core shown in FIG. 19.

[0073] In this embodiment, the IP core (IP3) is realized by three metallayers M1, M2 and m3. The metal layers M1 and M2 of the IP core aremainly used as signal lines and formed into thin wiring layers. Also,the uppermost layer (metal layer) M3 of the IP core is mainly used as acore power source line, thicker than the metal layers M1 and M2 andformed into a thick wiring layer.

[0074] In this embodiment, it is assumed that the metal layers M1 and M2have the same wiring width. In addition, the metal layer M3 has a largewidth on, for example, a portion used as the core power source line anda small wiring width on portions used as signal lines as in the case ofthe metal layers M1 and M2 as shown in FIG. 20. It is noted, however,that the portion of the metal layer used as the core power source linemay have a small width.

[0075] If this IP core is used in a design phase, the metal layers M1,M2 and M3 are used as they are and, as shown in FIGS. 21 and 22, metallayers M4, M5 and M6 are added, thereby forming a predeterminedfunctional block (circuit) in the chip.

[0076] Here, the metal layers M4 and M5 are mainly used as signal linesand formed into thin wiring layers as in the case of the metal layers M1and M2. The uppermost layer (metal layer) M6 of the semiconductor deviceis, on the other hand, mainly used as a chip power source line and padmetal and formed into a thick wiring layer as in the case of the metallayer M3.

[0077] As can be seen, the semiconductor device according to the presentinvention is characterized in that at least one of the intermediatelayers (wiring layers excluding the uppermost and lowermost layers)among a plurality of wiring layers is constituted out of a thick filmand that at least one wiring layer on the at least one intermediatelayer is constituted out of a thin film.

[0078] Namely, in the reference example, the thick wiring layer isformed on the thin wiring layer and no thin wiring layer is formed onthe thick wiring layer. According to the present invention, by contrast,a thin wiring layer can be formed on the thick wiring layer as required.

[0079] As a result, even if the uppermost layer of the IP core isconstituted out of a thick film so as to use the uppermost layer of theIP core as, for example, a core power source line, a wiring layer usedas signal line further above the uppermost layer of the IP core can beconstituted out of a thin film in the semiconductor device using this IPcore.

[0080] Furthermore, the core power source line can enhance theperformance of the IP core (functional block) and enables the wiringlayer on the uppermost layer of the IP core to be constituted out of athin film. Due to this, wiring efficiency can be enhanced and optimum IPdesigning and product development can be carried out.

[0081] 5. Fourth Embodiment

[0082]FIG. 23 shows an IP core. FIG. 24 shows one example of the devicestructure of the IP core shown in FIG. 23.

[0083] The IP core (IP4) in this embodiment has a different functionfrom that of, for example, the IP core shown in FIGS. 19 and 20.However, the number of metal layers and the thicknesses of therespective metal layers are common to the both IP cores.

[0084] The IP core (IP3) is realized by three metal layers M1, M2 andM3. The metal layers M1 and M2 of the IP core are mainly used as signallines and formed into thin wiring layers. Also, the uppermost layer(metal layer) M3 of the IP core is mainly used as a core power sourceline, thicker than the metal layers M1 and M2 and formed into a thickwiring layer.

[0085] In this embodiment, it is assumed that the metal layers M1 and M2have the same wiring width. Also, the metal layer M3 has a large widthon a portion used as, for example, the core power source line and, asshown in FIG. 24, a small wiring width on portions used as signal linesas in the case of the metal layers M1 and M2. It is noted, however, thatthe portion of the metal layer M3 used as the core power source line mayhave a small width.

[0086] If this IP core is used in a design phase, the metal layers M1,M2 and M3 are used as they are and, as shown in FIGS. 25 and 26, a metallayer M4 is added, thereby forming a predetermined functional block(circuit) in the chip. Here, the metal layer M4 is mainly used as signallines and formed into a thin wiring layer as in the case of the metallayers M1 and M2.

[0087] As can be seen, the semiconductor device according to the presentinvention is characterized in that at least one of the intermediatelayers (wiring layers excluding the uppermost and lowermost layers)among a plurality of wiring layers is constituted out of a thick filmand that at least one wiring layer on the at least one intermediatelayer is constituted out of a thin film.

[0088] Namely, in the reference example, the thick wiring layer isformed on the thin wiring layer and no thin wiring layer is formed onthe thick wiring layer. According to the present invention, by contrast,a thin wiring layer can be formed on the thick wiring layer as required.

[0089] As a result, even if the uppermost layer of the IP core isconstituted out of a thick film so as to use the uppermost layer of theIP core as, for example, a core power source line, a wiring layer usedas signal lines further above the uppermost layer of the IP core can beconstituted out of a thin film in the semiconductor device using this IPcore.

[0090] Furthermore, the core power source line can enhance theperformance of the IP core (functional block) and enables the wiringlayer on the uppermost layer of the IP core to be constituted out of athin film. Due to this, wiring efficiency can be enhanced and optimum IPdesigning and product development can be ensured.

[0091] In the meantime, according to the present invention, the numberof wiring layers and the thicknesses of the respective wiring layers arecommon to the IP core (IP3) shown in FIGS. 19 and 20 and the IP core(IP4) shown in FIGS. 23 and 24. Accordingly, as shown in, for example,FIGS. 27 and 28, even if the IP core (IP3) and the IP core (IP4) aremounted on one semiconductor chip to constitute one system, the layoutsof the respective IP cores can be utilized as they are. Due to this,design efficiency can be enhanced and semiconductor device developmentperiod can be thereby shortened.

[0092] 6. Others

[0093]FIG. 29 shows the relationship between the thicknesses of therespective wiring layers of the semiconductor device according to thepresent invention and those of the respective wiring layers of thesemiconductor device in the reference example.

[0094] It is assumed, for example, that the IP core is constituted outof m (where m is a natural number) wiring layers and a semiconductordevice using this IP core is constituted out of n (where n is a naturalnumber satisfying n>m) wiring layers. In this case, the thick wiringlayer is always formed on the lowermost thick wiring layer in thereference example. According to the present invention, by contrast, athin wiring layer can be formed on the lowermost thick wiring layer asrequired.

[0095]FIG. 30 shows an example in which four IP cores are mounted on onesemiconductor chip.

[0096] With such a system LSI, the uppermost layers Mm of the IP cores(IP1, IP2, IP4), for example, can be used as core power source lines,respectively, and the uppermost layer Mm of the IP core (IP3) can beused as signal lines. It is noted that the electrical connection of therespective IP cores can be established using wiring layers (e.g., M1 toMm) arranged in the spaces between the respective IP cores.Alternatively, the electrical connection can be established using wiringlayers (e.g., Mm+1 to Mn) on the wiring layers of the IP cores.

[0097] The present invention can be applied to any semiconductor devicesor particularly applied to semiconductor device using an IP core, e.g.,a logic LSI on which mixed memories are mounted and a system LSI.

[0098] Additional advantages and modifications will readily occur tothose skilled in the art. Therefore, the invention in its broaderaspects is not limited to the specific details and representativeembodiments shown and described herein. Accordingly, variousmodifications may be made without departing from the spirit or scope ofthe general inventive concept as defined by the appended claims andtheir equivalents.

What is claimed is:
 1. A semiconductor device comprising: asemiconductor substrate; a lowermost layer nearest to said semiconductorsubstrate; an uppermost layer farthest from said semiconductorsubstrate; and intermediate layers arranged between said lowermost layerand said uppermost layer; wherein when one of said intermediate layersis set as a first intermediate layer and the other one of saidintermediate layers is set as a second intermediate layer, said firstintermediate layer is on said lowermost layer side compared with saidsecond intermediate layer and said first intermediate layer is thickerthan said second intermediate layer.
 2. The semiconductor deviceaccording to claim 1, wherein a wiring pitch of said first intermediatelayer is wider than a wiring pitch of said second intermediate layer. 3.The semiconductor device according to claim 1, wherein said firstintermediate layer is a layer on which a power source line is formed. 4.The semiconductor device according to claim 1, wherein said firstintermediate layer comprises a first area having signal lines and asecond area having power source lines, and a pitch of said power sourcelines is wider than that of said signal lines.
 5. The semiconductordevice according to claim 1, wherein said first intermediate layercomprises a first area having signal lines and a second area havingpower source lines, and a width of each of said power source lines iswider than that of said signal lines.
 6. The semiconductor deviceaccording to claim 1, wherein said first intermediate layer issubstantially as thick as said uppermost layer.
 7. The semiconductordevice according to claim 1, wherein said second intermediate layer issubstantially as thick as said lowermost layer.
 8. The semiconductordevice according to claim 1, wherein all of said uppermost layer, saidlowermost layer and said intermediate layers are metal layers.
 9. Asemiconductor device comprising: a semiconductor substrate; an IP corearea on said semiconductor substrate; a peripheral area on saidsemiconductor substrate except for said IP core area; a lowermost layernearest to said semiconductor substrate; an uppermost layer farthestfrom said semiconductor substrate; and intermediate substrates arrangedbetween said lowermost layer and said uppermost layer; wherein when oneof said intermediate layers is set as a first intermediate layer and theother one of said intermediate layers is set as a second intermediatelayer, said first intermediate layer is on said lowermost layer sidecompared with said second intermediate layer and said first intermediatelayer is thicker than said second intermediate layer.
 10. Thesemiconductor device according to claim 9, wherein said uppermost layerand all the intermediate layers between said first intermediate layerand said uppermost layer are formed only in said peripheral area, andsaid first intermediate layer is an uppermost layer farthest to saidsemiconductor substrate in said IP core area.
 11. The semiconductordevice according to claim 10, wherein said first intermediate layer is alayer on which a core power source line is formed in said IP core area.12. The semiconductor device according to claim 9, wherein a wiringpitch of said first intermediate layer is wider than a wiring pitch ofsaid second intermediate layer.
 13. The semiconductor device accordingto claim 9, wherein said first intermediate layer is substantially asthick as said uppermost layer.
 14. The semiconductor device according toclaim 9, wherein said second intermediate layer is substantially asthick as said lowermost layer.
 15. The semiconductor device according toclaim 9, wherein said first intermediate layer comprises a first areahaving signal lines and a second area having power source lines, and apitch of said power source lines is wider than that of said signallines.
 16. The semiconductor device according to claim 9, wherein saidfirst intermediate layer comprises a first area having signal lines anda second area having power source lines, and a width of each of saidpower source lines is wider than that of said signal lines.
 17. Thesemiconductor device according to claim 9, wherein all of said uppermostlayer, said lowermost layer and said intermediate layers are metallayers.